DC-DC converters or regulators are implemented in circuits to achieve a desired source voltage. A buck switching regulator is a non-linear DC to DC voltage converter. The buck switching regulator has a pair of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) having a common switch node. A gate control circuit in the buck switching regulator controls the pair of MOSFETs connected to an LC filter circuit. The gate control circuit controls timing of the pair of MOSFETs to convert an input voltage Vin to an output voltage Vout. A first switch among the pair of MOSFETs generates a pulsated voltage signal. The pulsated voltage signal is filtered by the LC filter circuit to generate the output voltage Vout. A second switch among the pair of MOSFETs is switched ON to provide a conduction path necessary to de-energize an inductor in the LC filter during each switching cycle. Switching OFF the second switch before the inductor is completely de-energized results in energy loss in the buck switching regulator. As a result, a circuit for identifying an instance when the inductor current is zero is necessary. An instance when the inductor current becomes zero is referred to as “trip point”. A zero current detector is used to identify the instance at which the inductor current is zero.
Referring to FIG. 1 now, FIG. 1 illustrates an example of an existing buck switching regulator circuit 100 implementing a zero current detect (ZCD) comparator 110. The buck switching regulator 100 includes a controller 105, the ZCD comparator 110, a gate control circuit 115, a first switch 120, a second switch 125, an inductor 130, a capacitor 135, and a load terminal 140. The first switch 120 and the second switch 125 have a common switch node. A first reference voltage VREF1 and a switch node voltage SW_OUT is fed to the ZCD comparator 110. The first reference voltage VREF1 represents estimated magnitude of the switch node voltage SW_OUT when current through the inductor 130 is zero. A second reference voltage VREF and an output voltage Vout is fed to the controller 105. The controller 105 controls duty cycle of the buck switching regulator 100. The output voltage Vout is proportional to the duty cycle of the buck switching regulator 100.
The working of the buck switching regulator 100 in FIG. 1 is explained with reference to voltage signal graphs depicted in FIG. 2. FIG. 2 depicts variation in the output of the ZCD comparator 110 based on the switch node voltage SW_OUT. The gate control circuit 115 supplies a PON signal to a gate terminal of the first switch 120. The gate control circuit 115 supplies an NON signal to a gate terminal of the second switch 125. The variations of the PON signal and the NON signal with time is depicted in FIG. 2. The PON signal goes to the HIGH state at a first instance t1. The PON signal switches on the first switch 120 at the first instance t1. The first switch 120 provides a low resistance conduction path from supply voltage Vdd to the inductor 130. The switch node voltage SW_OUT signal rises to the supply voltage Vdd at the first instance t1. The gate control circuit 115 lowers the PON signal to a LOW state at a second instance t2. The PON signal hence switches OFF the first switch 120. The first switch 120 breaks the low resistance conduction path from the supply voltage Vdd to the inductor 130. The inductor 130 resists the abrupt change in current and forward biases a parasitic diode in the second switch 125 and hence the switch node voltage SW_OUT signal drops to negative value of forward bias voltage of the parasitic diode.
The gate control circuit 115 shifts the NON signal to HIGH state at a third instance t3. Time elapsed between the second instance t2 and the third instance t3 is called non-overlap period. The non-overlap period prevents the formation of a short circuit through the first switch 120 and the second switch 125. The second switch 125 provides a conduction path from the inductor 130 to ground. At the third instance t3, the inductor current flows through the second switch 125 to ground de-energizing the inductor 130. Therefore the switch node voltage SW_OUT increases to a value almost equal to zero. After the third instance t3 the switch node voltage SW_OUT starts gradually increasing at the third instance t3 due to linear de-energization of the inductor 130. At a fourth instance t4, the switch node voltage SW_OUT equals the first reference voltage VREF1. The ZCD comparator 110 changes a ZCD Output signal to HIGH state after a comparator delay time td1. At a fifth instance t5, the gate control circuit 115 changes the NON signal to LOW state. Thus the ZCD comparator 110 identifies a trip point when the inductor current is zero and switches OFF the second switch 125 at the instance.
However, accuracy of the trip point of the ZCD comparator 110 depends on variables such as input supply, output voltage, comparator delay, mismatch in internal reference values, path delays, output inductance of the buck switching regulator 100 and, routing resistance of the buck switching regulator 100. If the trip point occurs before inductor current falls to zero, a positive non-zero current remains in the inductor 130 when the second switch 125 is turned OFF. The remaining inductor current passes through a parasitic diode in the second switch 125 and cause conduction losses. If the trip point occurs after the inductor current cross a zero value, a negative non-zero current remains in the inductor 130 when the second switch 125 is turned OFF. Negative non-zero inductor current during the conduction time of the second switch 125 causes energy loss. The variation of the trip point affects energy efficiency of the buck switching regulator 100.
In light of the foregoing discussion, there is a need for a regulator circuit to control the variations in trip point for switching OFF a power switch in the switching regulator circuit.